The present invention generally relates to memory devices, and, more particularly, to a read-only memory (ROM) device having single transistor memory cells that store two bits of data.
ROM devices are used for storing data by various electronic devices. A ROM device typically includes bit-lines, virtual ground lines, and an array of memory cells that each store a single bit of data. ROM devices retain the stored data even when the power of the electronic device is turned OFF. Typically, ROM devices are used to store data that does not require frequent updates.
Data can be stored or the ROM device is programmed during manufacturing. For example, data may be stored/programmed during the ion diffusion process of the semiconductor substrate of the ROM device. In another example, data may be stored during a metallization process of the ROM device. In yet another example, data is stored during a via formation process of the ROM device.
One way to achieve higher density is to reduce the width of the memory cells of the ROM device. However, one consequence of the reduced width is that the ROM device cannot operate at low input voltages. Thus, for low voltage devices, it is preferred not to decrease the width of the memory cells, which results in low density. One known technique to increase density is to store two bits of bit data in a single memory cell, as shown in FIG. 1, and also as described in U.S. Pat. Nos. 9,202,588 and 9691,496, each of which is herein incorporated by reference.
FIG. 1 is a schematic circuit diagram of a conventional ROM device 100 that includes first through fourth transistors 102-108 and a virtual ground generation circuit (VGGC) 110. The first through fourth transistors 102-108 constitute first through fourth memory cells. The ROM device 100 further includes first and second bit-lines BL0 and BL1, a virtual ground line VGND, and first through fourth word lines WL0-WL3. Each of the word lines WL0-WL3 is connected to output lines of an address decoder (not shown) for switching ON one of the transistors 102-108. The first and second bit-lines BL0 and BL1 and the virtual ground line VGND are connected to the VGGC 110. The VGGC 110 controls voltage levels of the first and second bit-lines BL0 and BL1 to perform a read operation, such that one bit of the data stored in the transistors 102-108 can be read at a time. The first through fourth transistors 102-108 are arranged in a column between the first and second bit-lines BL0 and BL1. Each of the transistors 102-108 stores two bits of data depending on the connections of the transistors 102-108 with the first and second bit-lines BL0 and BL1, and the virtual ground line VGND.
The first transistor 102 has a source connected to the first bit-line BL0 and a drain connected to the virtual ground line VGND. The first transistor 102 stores bits “10” based on the connection of its source and drain terminals with the first bit-line BL0 and the virtual ground line VGND, respectively. The first transistor 102 has a gate connected to the first word-line WL0. To read the data stored in the first transistor 102, an address decoder activates the first word-line WL0, which in turn switches ON the first transistor 102.
The second transistor 104 has a source connected to the second bit-line BL1 and a drain connected to the virtual ground line VGND. The second transistor 104 stores bits “01” based on the connection of its source and drain terminals with the second bit-line BL1 and the virtual ground line VGND, respectively. The second transistor 104 has a gate connected to the second word-line WL1. To read the data stored in the second transistor 104, the address decoder activates the second word-line WL1, which in turn switches ON the second transistor 104.
The third transistor 106 has a source connected to the first bit-line BL0 and a drain terminal to the second bit-line BL1. The third transistor 106 stores bits “00” based on the connection of its source and drain terminals with the first bit-line BL0 and the second bit-line BL1, respectively. The third transistor 106 has a gate connected to the third word-line WL2. To read the data stored in the third transistor 106, the address decoder activates the third word-line WL2, which in turn switches ON the third transistor 106.
The fourth transistor 108 has source and drain terminals that are not connected to any of either the first and second bit-lines BL0 and BL1, or the virtual ground line VGND. The fourth transistor 108 stores bits “11”. The fourth transistor 108 has a gate connected to the fourth word-line WL4. To read the data stored in the fourth transistor 108, the address decoder activates the fourth word-line WL4, which in turn switches ON the fourth transistor 108.
The ROM device 100 uses two bit-lines for a single memory cell. Thus, the width of each of the first through fourth memory cells 102-108 is greater than corresponding minimum processing widths. Hence, the ROM device 100 can be operated at low input voltages. However, the density of the ROM device 100 could be improved if the number of bit lines could be reduced. It would be advantageous to have a higher density ROM device.